"Scaling to nanometer levels and simultaneously sustaining Moore's law pose a number of challenges such as parameter variations, noise and various device perturbations. Such probabilistic or statistical behavior occurs at device level of every transistor. In order to address the critical requirement, a modern approach to statistical designs and error tolerance in the form of a new set of probabilistic architectures, referred to as probabilistic system-on-a-chip (PSOC) is being implemented."
The report highlights the development of probabilistic complementary metal-oxide semiconductor (PCMOS) technology, and also illustrates the energy savings at the device level and considerable performance and energy advantages at the application level. In addition, the report briefs about the PSOC architecture focusing on harnessing probabilistic behavior of a PCMOS device to develop architectural primitives featuring definite statistical behaviors.